1. Field
Example embodiments of the following description provide a memory protection apparatus and method in a multi-processor system, and more particularly, to a memory protection apparatus and method that may restrict a memory access of each processor with respect to a shared memory in a multi-processor system.
2. Description of the Related Art
A conventional memory protection technology is broadly classified into a Memory Management Unit (MMU)-based scheme and a segment-based scheme. In the MMU-based scheme, a memory may be divided into pages of equal size, and may be managed. Additionally, the MMU may describe, in a page table, mapping of a logical address and a physical address, and may perform address translation based on the mapping. When the mapping is not performed, or an access right is violated during the address translation, the MMU may notify a Central Processing Unit (CPU) that the mapping is not performed or that the access right is violated. When address translation is performed based on a page table located in a memory, memory access is attempted several times in order to perform a single memory access. In the MMU, to quickly perform the address translation, a cache for a page table, called a Translation Lookaside Buffer (TLB), may be maintained. Since the TLB enables a fast access, differently from a Dynamic Random Access Memory (DRAM), an implementation overhead caused by the address translation may be reduced.
However, the MMU-based scheme is not suitable for an embedded multi-processor system. First, complex hardware logic is required for the MMU and the TLB. Additionally, to maintain the page table, a separate memory is required. In the embedded multi-processor system, each CPU has its fast local memory. However, it is difficult to maintain the page table due to the small size of each fast local memory. Additionally, when the page table is placed in a shared DRAM, and when there is no separate hardware, such as a TLB, it is difficult to achieve a high performance. Such hardware needs to be realized for each of the multiple cores and accordingly, overhead may be increased, as the number of cores is increased.